1. Field of the Invention
The present invention relates to a semiconductor device of high-voltage CMOS structure, and a method of fabricating such a semiconductor device of high-voltage CMOS structure.
2. Description of the Related Art
Heretofore, semiconductor devices of CMOS (Complementary Metal Oxide Semiconductor) structure comprising a pair of P- and N-type MOS transistors formed on a single SOI (Silicon-On-Insulator) substrate have been used in various applications. Such semiconductor devices of CMOS structure are available in a variety of types. CMOS circuits for use as plasma display panel drive circuits need to withstand high voltages. It has been proposed to employ an offset structure for P- and N-type MOS transistors in such CMOS circuits.
One conventional semiconductor device of CMOS structure will be described below with reference to FIGS. 1 through 5(b) of the accompanying drawings. FIG. 1 is a fragmentary vertical cross-sectional view showing a multilayer structure of a CMOS circuit as the conventional semiconductor device, and FIGS. 2(a) through 5(b) are fragmentary vertical cross-sectional views illustrative of successive steps of a process of fabricating the CMOS circuit shown in FIG. 1.
The conventional semiconductor device will be described on the assumption that layers are successively formed on a substrate in an upward direction. Such a direction is employed by way of example only for the sake of brevity, and will not limit any direction in which the semiconductor device is actually fabricated and used. Layers or films with a higher concentration are indicated by P.sup.+ and N.sup.+, and those with a lower concentration are indicated by P.sup.- and N.sup.-. In FIGS. 1 through 5(b) and other figures, "P+", "N+", "P-", "N-" should be construed to mean "P.sup.+ ", "N.sup.+ ", "P.sup.- ", "N.sup.- ", respectively.
As shown in FIG. 1, a CMOS circuit 1 has a single SOI substrate 2 of a P-type which is a first conductivity type. On the SOI substrate 2, there are disposed a P-channel first transistor 3 of the first conductivity type and an N-channel second transistor 4 of a second conductivity type. Each of the first and second transistors 3, 4 is of an offset LMOS (Lateral MOS) structure.
The SOI substrate 2 comprises first and second substrates 5, 6 each of the P.sup.- -type which is the first conductivity type. The first and second substrates 5, 6 are integrally joined to each other by an embedded oxide film 7. The first and second transistors 3, 4 are disposed in only the first substrate 5 that is positioned above the embedded oxide film 7. The first and second transistors 3, 4 are isolated from each other by a trench 8 and a laminated oxide film 9.
The P-channel first transistor 3 comprises a source 11, a gate 12 positioned inside of the source 11, and a drain 13 positioned centrally therein. The source 11, the gate 12, and the drain 13 are positioned on a single N.sup.- -type well 14 disposed in the first substrate 5.
The source 11 of the first transistor 3 comprises a P-type source diffusion layer 21 positioned on the N.sup.- -type well 14, a P.sup.+ -type source contact diffusion layer 22 positioned on an upper surface of the P-type source diffusion layer 21, and an N.sup.+ -type back-gate contact diffusion layer 23 positioned on the N.sup.- -type well 14 outside of the P.sup.+ -type source contact diffusion layer 22. A source electrode 24 is positioned on the contact diffusion layers 22, 23.
The drain 13 of the first transistor 3 comprises a P-type drain offset diffusion layer 25 positioned on the N.sup.- -type well 14 and a P.sup.+ -type drain contact diffusion layer 26 positioned centrally on an upper surface of the P-type drain offset diffusion layer 25. A drain electrode 27 is positioned on the P.sup.+ -type drain contact diffusion layer 26.
The drain offset diffusion layer 25 and the source diffusion layer 21 project from the respective contact diffusion layers 26, 22 toward the gate 12, and a field oxide film 28 is positioned on upper surfaces of the offset regions of the drain offset diffusion layer 25 and the source diffusion layer 21. A gate electrode 29 is positioned on an upper surface of the field oxide film 28 which doubles as a gate oxide film, and a gate extension electrode 30 is positioned on an upper surface of the gate electrode 29.
The N-channel second transistor 4 is disposed in juxtaposed relation to the P-channel first transistor 3. The N-channel second transistor 4 has a source 41, a gate 42 positioned inside of the source 41, and a drain 43 positioned centrally therein.
In the source 41 of the second transistor 4, the P.sup.- -type first substrate 5 serves as a source base layer 50, and a P-type source shield diffusion layer 51 is positioned on the source base layer 50. An N.sup.+ -type source contact diffusion layer 52 and an P.sup.+ -type back-gate contact diffusion layer 53 are positioned respectively on inner and outer regions of an upper surface of the source shield diffusion layer 51. A source electrode 54 is positioned on the contact diffusion layers 52, 53.
In the drain 43 of the second transistor 4, an N-type drain offset diffusion layer 55 is disposed in the P.sup.- type first substrate 5. An N.sup.+ -type drain contact diffusion layer 56 is positioned centrally on an upper surface of the offset diffusion layer 55. A drain electrode 57 is positioned on the drain contact diffusion layer 56.
The drain offset diffusion layer 55 and the source shield diffusion layer 51 project from the respective contact diffusion layers 56, 52 toward the gate 42, and a field oxide film 58 and a gate oxide film 59 are positioned on upper surfaces of the offset regions of the drain offset diffusion layer 55 and the source shield diffusion layer 51. A gate electrode 60 is positioned on an upper surface of the oxide films 58, 59, and a gate extension electrode 61 is positioned on an upper surface of the gate electrode 60.
The electrodes 24, 27, 30, 54, 57, 61 of the first and second transistors 3, 4 extend through the laminated oxide film 9 on which an isolation layer (not shown) is positioned. The isolation layer is partly removed to expose the electrodes 24, 27, 30, 54, 57, 61, which provide connection pads (not shown).
In the CMOS circuit 1 of the above structure, since both the P-channel first transistor 3 and the N-channel second transistor 4 are of an LMOS structure, currents flow laterally from the source electrodes 24, 54 through the gates 12, 42 to the drain electrodes 27, 57.
Furthermore, both the transistors 3, 4 are of an offset structure in which the drain offset diffusion layers 25, 55 extend to lower surfaces of the field oxide film 28 and the field and gate oxide films 58, 59. Therefore, the breakdown voltage of these transistors 3, 4 is so high that the transistors 3, 4 are capable of switching high voltages.
A process of fabricating the CMOS circuit 1 will briefly be described below with reference to FIGS. 2(a) through 5(b).
As shown in FIG. 2(a), first and second substrates 5, 6 of P.sup.- -type silicon are prepared, and integrally joined to each other by an embedded oxide film 7 in the form of an SIO.sub.2 film having a thickness of about 2 .mu.m. The first substrate 5 is ground to a thickness of about 5 .mu.m, thus producing a single SOI substrate 2.
Then, as shown in FIG. 2(b), a thermal oxide film (not shown) is formed on the entire upper surface of the first substrate 5, and patterned into a mask 71 of predetermined shape. An impurity of phosphorus is introduced into the first substrate 5 through openings of the mask 71 by ion implantation. The assembly is heated to diffuse the introduced phosphorus down to the upper surface of the embedded oxide film 7, for thereby simultaneously forming an N.sup.- -type well 14 of a first transistor 3 and a drain offset diffusion layer 55 of a second transistor 4.
Then, as shown in FIG. 3(a), after the mask 71 is removed, a mask 72 of another shape is formed. An impurity of boron is then introduced into the first substrate 5 through openings of the mask 72 by ion implantation. The assembly is heated to diffuse the introduced boron to a depth ranging from 1 to 2 .mu.m from the surface of the first substrate 5, for thereby simultaneously forming a P-type source diffusion layer 21 and a drain offset diffusion layer 25 of the first transistor 3 and a source shield diffusion layer 51 of the second transistor 5.
Thereafter, the mask 72 is removed, and then a mask of predetermined shape (not shown) is formed of nitride. As shown in FIG. 3(b), field oxide films 28, 58 are formed to a thickness ranging from 0.5 to 1.0 .mu.m by LOCOS (Local Oxidation of the Surface or Local Oxidization of Silicon).
A thermal oxide film and a polysilicon film are formed on the entire surface formed thus far according to CVD (Chemical Vapor Deposition), and an impurity of phosphorus is diffused to make the polysilicon film electrically conductive. As shown in FIG. 4(a), the electrically conductive polysilicon film and the thermal oxide film are then patterned at the same time, thus forming a gate oxide film 59 of the second transistor 3 with the thermal oxide film and gate electrodes 29, 60 of the first and second transistors 3, 4 with the electrically conductive polysilicon film.
Masks of predetermined shape (not shown) are then formed, and phosphorus and boron are introduced into various regions thereby to form contact diffusion layers 22, 23, 26, 52, 53, 56 of the first and second transistors 3, 4 as shown in FIG. 4(b).
Then, as shown in FIG. 5(a), an oxide film having a thickness of 100 nm is formed by CVD and patterned into a mask 73. Thereafter, trenches 8 are formed around the first and second transistors 3, 4 by silicon etching through the mask 73. As shown in FIG. 5(b), a laminated oxide film 9 is deposited to a thickness ranging from 1 to 2 .mu.m in order to fill up the trenches 8, thus isolating the first and second transistors 3, 4 from each other.
Thereafter, as shown in FIG. 1, contact holes are defined in the laminated oxide film 9, and electrodes 24, 27, 30, 54, 57, 61 of the first and second transistors 3, 4 are formed to a thickness ranging from 0.5 to 2.0 .mu.m by sputtering aluminum or the like. In this manner, a CMOS circuit 1 is completed.
In the CMOS circuit 1, both the P-channel first transistor 3 and the N-channel second transistor 4 are of an offset LMOS structure for increasing the breakdown voltage thereof. Actually, however, the breakdown voltage of the P-channel first transistor 3 is lower than that of the N-channel second transistor 4, and has a high on-state resistance.
The breakdown voltage of the first transistor 3 is governed by the joined state between the drain offset diffusion layer 25 and the N.sup.- -type well 14, and the breakdown voltage of the second transistor 4 is governed by the joined state between the drain offset diffusion layer 55 and the source base layer 50. The breakdown voltage of the second transistor 4 is stable because the impurity is diffused only into the drain offset diffusion layer 55 which is joined to the source base layer 50.
In the first transistor 3, the N.sup.- -type well 14 formed by diffusing phosphorus into the P.sup.- -type first substrate 5 and the P-type drain offset diffusion layer 25 formed by diffusion of boron into the N.sup.- -type well 14 are joined to each other. Therefore, the impurities are diffused to form both the layers 14, 25, and the impurities are diffused twice to form the layer 25. As a result, it is difficult to stabilize the breakdown voltage of the first transistor 3.
The breakdown voltage of the first and second transistors 3, 4 also depends on the radii of curvature of the above joined boundaries. The drain offset diffusion layer 25 of the first transistor 3 is shallower than the drain offset diffusion layer 55 of the second transistor 4. Therefore, the radius of curvature of the joined boundary of the drain offset diffusion layer 25 is smaller than the radius of curvature of the joined boundary of the drain offset diffusion layer 55. Accordingly, the breakdown voltage of the first transistor 3 is relatively low in view of the smaller radius of curvature of the joined boundary of the drain offset diffusion layer 25.
Inasmuch as the breakdown voltage of the first transistor 3 is low, the drain offset diffusion layer 25 cannot be reduced in size. Thus, the area occupied by the first transistor 3 cannot be reduced in size. For this reason, it is difficult to reduce the overall chip area of the CMOS circuit 1. The amount of the material of the SOI substrate 2 which is complex in structure and expensive cannot be cut down, and it is difficult to increase the productivity of the CMOS circuit 1.
In addition, while the second transistor 4 has a low on-state resistance because a drain current flows through the drain offset diffusion layer 55 that is wide and deep, the on-state resistance of the first transistor 3 is high as the drain offset diffusion layer 25 for a drain current to flow therethrough is narrow and shallow.